Power-rail ESD clamp circuit for mixed-voltage I/O buffer

ABSTRACT

A power-rail ESD clamp circuit for mixed-voltage I/O buffer is proposed. The power-rail ESD clamp circuit comprises an ESD detection circuit and an ESD protection device. Under normal operating condition, the ESD detection circuit will not trigger the ESD protection device, and therefore the component used in the circuit will not have the gate-oxide reliability issue and also will not generate undesirable leakage current. Under ESD-zapping conditions, the ESD detection circuit will provide some trigger voltage or current to bias the ESD protection device. The ESD protection device can be triggered on quickly to discharge the ESD energy efficiently.

1. Field of the Invention

The present invention relates to a power-rail ESD clamp circuit formixed-voltage I/O buffer, and more particularly, to a power-clamp ESDprotection circuit with only 1-V and 2.5-V devices to operate at a 3.3-Vpower supply voltage

2. Background of the Invention

To improve circuit operating speed and performance, the devicedimensions of MOSFET have been shrunk in the advanced deep-submicronintegrated circuits. In order to follow the constant-field scalingrequirement and to reduce the power consumption, the power-supplyvoltages in ICs have also been scaled downwards. So, mostmicroelectronic systems require the interfacing of semiconductor chipsor subsystems with different internal power-supply voltages. With themix of power-supply voltages, chip-to-chip interface I/O circuits mustbe designed to avoid electrical overstress across the gate oxide, toavoid hot-carrier degradation on the output devices, and to preventundesirable leakage current paths between the chips.

Refer to FIG. 1 which is a schematic diagram showing a conventional I/Obuffer for an electronic system with independent power supply. As seenin FIG. 1, the electronic system 100 with independent power supplycomprises an output stage and an input stage, wherein the VDD used inthe internal circuit of the input stage 120 is the same as that used inthe internal circuit of the output stage 110, and the VDD is assumed tobe 1V hereinafter, and an I/O pad 140 used for receiving signals fromother electronic system with different power supply (not shown). Hence,the I/O pad 140 is capable of receiving signals from other electronicsystem with different independent power supply and feeding the same tothe internal circuit of the input stage 120.

Since the thin gate oxide of both the output PMOS 150 and the outputNMOS 160 for input electrostatic discharge (ESD) protection is designedto withstand only 1-V, therefore, when an external 3.3-V signal isapplied to the I/O pad 140, the output PMOS 150 will cause the leakagecurrent paths from the I/O pad 140 to VDD, and the output NMOS 160 areoverstressed by the 3.3-V input signal and will cause gate oxidereliability problem. To solve the gate-oxide reliability issue withoutusing the additional thick gate oxide process (also known as dual gateoxides in some CMOS processes), the stacked-MOS configuration has beenwidely used in the mixed-voltage I/O buffers, and in the power-rail ESDclamp circuits.

However. Similar condition can be seen in a power-rail ESD circuit formixed-voltage I/O buffer disposed in ICs. For instance, the electronicsystem 100 seen in FIG. 1 is an mixed-voltage I/O buffer with differentVCC and VDD.

FIG. 2 illustrates an ESD protection device for mixed-voltage I/O bufferagainst ESD damage. The ESD protection device 200 contains two NMOStransistors 210, 220 stacked in a cascade configuration. The two NMOStransistors are thin-gate oxide device. The drain of the firsttransistor 210 (top NMOS transistor) is connected to an VCC (3.3-V) andits gate (top gate) is connected to the lower power supply (VDD) in theESD protection device 200. The source of the first transistor 210 andthe drain of the second transistor 220 (bottom NMOS transistor) aremerged together. The gate (bottom gate) and the source of the secondtransistor 220 are connected to the ground plane of the ESD protectiondevice 200. This configuration allows this device to easily solve theissue of thin gate oxide reliability during the normal operation whileproviding a parasitic lateral NPN for bipolar action during ESD event.

However, the shortcomings of the ESD protection device 200 are that thestacked NMOS transistors 210, 220 have inferior current drivencapability, and are less capable of discharging ESD current so as tohave worse ESD endurance.

In view of the above description, the present invention provides apower-rail ESD clamp circuit for mixed-voltage I/O buffer not onlycapable of solving the issue of thin gate oxide reliability, but alsowith better ESD endurance and faster turn-on speed.

SUMMARY OF THE INVENTION

The primary object of the invention is to provide a power-rail ESD clampcircuit for mixed-voltage I/O buffer comprising an ESD detection circuitand an ESD protection device, wherein the ESD detection circuit furthercomprises a first resistor, a second resistor, a capacitor, a first PMOStransistor, a second PMOS transistor, a third PMOS transistor, and afirst NMOS transistor.

The first resistor has a first end and a second, wherein the first endthereof is connected to a first node coupled to both an I/O pad and afirst voltage. The capacitor also has a first end and a second end,wherein the first end thereof is connected to a second node coupled tothe second end of the first resistor. The second resistor also has afirst end and a second end, wherein the first end thereof is connectedto a second voltage. The first PMOS transistor has a gate, a drain and asource, wherein the gate thereof is connected to both a third node andthe second resistor, and the drain thereof is connected to a fourth nodecoupled to the ground, and the source thereof is connected to the secondend of the capacitor. The second PMOS transistor also has a gate, adrain and a source, wherein the gate thereof is connected to the secondnode, and the source thereof is connected to the first node. The thirdPMOS transistor also has a gate, a drain and a source, wherein the gatethereof is connected to the third node, and the source thereof isconnected to the drain of the second PMOS transistor. The first NMOStransistor also has a gate, a drain and a source, wherein the gatethereof is connected to the third node, and the drain is connected to afifth node coupled to the drain of the third PMOS transistor.

The ESD protection device comprises a first end, a second end and atrigger end, wherein the first end thereof is connected to the firstnode, and the second end thereof is connected to the fourth node, andthe trigger end thereof is connected to the fifth end.

In a preferred embodiment of the present invention, the first PMOStransistor, the second PMOS transistor and the third PMOS transistor are2.5-V PMOS transistors and the NMOS transistor is a 1-V NMOS transistor.

To prevent the first NMOS transistor from being turn-on underESD-zapping condition, a second NMOS transistor is being added anddisposed between the first NMOS transistor and the ESD protection deviceaccording to another preferred embodiment of the present invention.Therefore, the first PMOS transistor, the second PMOS transistor and thethird PMOS transistor are 2.5-V PMOS transistors and the NMOS transistoris a 1-V NMOS transistor, or the first PMOS transistor, the second PMOStransistor and the third PMOS transistor are 2.5-V PMOS transistors andthe NMOS transistor and the second NMOS transistor are 1-V NMOStransistors.

The ESD protection device is equivalent to a NPN transistor, such that,in a preferred embodiment of the present invention, the ESD protectiondevice can be a field oxide device (FOD), a stacked NMOS configuration,or a silicon controlled rectifier (SCR) with diode string.

To sum up, the present invention provides a provides a power- rail ESDclamp circuit for mixed-voltage I/O buffer not only capable of solvingthe issue of thin gate oxide reliability, but also with better ESDendurance and faster turn-on speed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram showing a conventional I/O buffer for anelectronic system with independent power supply.

FIG. 2 illustrates an ESD protection device for mixed-voltage I/O bufferagainst ESD damage.

FIG. 3 is a schematic diagram showing a power-rail ESD clamp circuit formixed-voltage I/O buffer according to a preferred embodiment of thepresent invention.

FIG. 4 is another preferred embodiment of the present invention using aFOD as the ESD protection device of FIG. 3

FIG. 5 is a schematic diagram showing a power-rail ESD clamp circuit formixed-voltage I/O buffer according to another preferred embodiment ofthe present invention.

FIG. 6 is a schematic diagram showing a power-rail ESD clamp circuitusing a thin gate oxide NMOS transistor instead of the thick gate oxideNMOS transistor of FIG. 5.

FIG. 7 and FIG. 8 respectively is the spice simulation of FIG. 4 undernormal VCC power-on transition and under PS-mode ESD-zapping condition.

FIG. 9 shows another embodiment of the power-rail ESD protection circuitusing where stacked NMOS configuration as the ESD protection device.

FIG. 10 shows yet another embodiment of the power-rail ESD protectioncircuit using stacked NMOS configuration as the ESD protection device.

FIG. 11 shows yet another embodiment of the power-rail ESD protectioncircuit using SCR as the ESD protection device.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The invention discloses a power-rail ESD clamp circuit for mixed-voltageI/O buffer capable of solving solve the gate-oxide reliability issue andpreventing undesirable leakage current paths between the chips withoutusing the additional thick gate oxide process.

In this regard, the present invention provides a power-clamp ESDprotection circuit using both thick gate oxide devices and thin gateoxide device simultaneously so as to improve the reliability and theelectrical characteristic of the ESD protection circuit.

Please refer to FIG. 3, which is a schematic diagram showing apower-rail ESD clamp circuit for mixed-voltage I/O buffer according to apreferred embodiment of the present invention. The power-rail ESD clampcircuit as seen in FIG. 3 is consisted of an ESD detection circuit 310and an ESD protection device 320, wherein the ESD detection circuit 310further comprises two resistors 311, 312, a capacitor 313, three PMOStransistor 314, 315, 316 and a NMOS transistor 317.

The ESD detection circuit 310 is primarily being used for triggering onthe ESD protection device 320 while detecting an ESD-zapping conditionbetween the VCC and the VSS. The function of ESD detection circuit 310is inactive and doesn't affect the operations of other internal circuitstherein under normal operating condition. While an ESD-zapping conditionis happening between the VCC and the VSS, the function of ESD detectioncircuit 310 is active so as to trigger on the ESD protection device 320quickly and discharge the ESD-generated current.

Assuming the voltage VDD of FIG. 3 is 1V and the voltage VCC of FIG. 3is 3.3V, and the PMOS transistors are 2.5-V PMOS transistors and theNMOS transistor 317 is a 1-V NMOS transistor, therefore, under normaloperating condition, the capacitor 313 is off and the voltage of node 1coupled to the resistor 311, the VCC and the source of the PMOStransistor 314 is equal to the voltage of node 2 coupled to thecapacitor 313 and the gate of the PMOS transistor 314, i.e. 3.3V.

When the 3.3-V power supply is powered on, the voltages at node 1 andnode 2 are both 3.3V under normal operating condition, and the voltageat the source of the PMOS transistor 314 is equal to that at the gate ofthe same that both are smaller than an active voltage, i.e.|V_(gs)|<|V_(t)|, and the gate of the PMOS transistor 314 is biased at3.3V through the resistor 312. The sources of the PMOS transistor 314and the PMOS transistor 315 will be biased at ˜1V in the steady statebecause their gates are biased at 1V. Therefore, the PMOS transistor 314and the PMOS transistor 315 are inactive in the steady state and theNMOS transistor 317 is active since the voltage at node 3 coupled toboth the gate of the PMOS transistor 315 and the gate of the NMOStransistor 317 is biased at 1V. The drain of the NMOS transistor 317coupled to node 4 will be biased at zero voltage due to the conductivityof the NMOS transistor 317 such that the voltage at node 5 coupled tothe drain of the PMOS transistor 315, the drain of the NMOS transistor317 and the trigger end of the ESD protection device 320 will also dropto zero voltage.

Therefore, the voltage at node 5 is 0-V such that the ESD detectioncircuit 310 will not trigger on the ESD protection device 320. Moreover,The voltage drops on the gate oxides (|Vgs| and |vgd|) of the PMOStransistor 314, 315, and 316, are smaller than 2.5V, and the voltagedrops on the gate oxide (|Vgs| and |Vgd|) of the NMOS transistor 317 aresmaller than 1V. No gate oxide reliability issue and steady leakagecurrent exist in such power-clamp ESD protection circuit.

When the ESD event is applied to the VCC line with VSS grounded andother nodes are floating, the gate of the PMOS transistor 314 is kept atlow voltage level due to the RC delay, so the PMOS transistor 314 isturned on to raise the source voltage of PMOS transistor 315 due to theESD energy. The RC time constant is designed to distinguish the VDDpower-on event (with a rise time of ˜ms) from the ESD-stress events(with a rise time of ˜ns). During the normal VCC power-on transition(from low to high), the gate voltage of the PMOS transistor 314 canfollow up in time with the power-on VCC signal, i.e. the voltage at node2 can match in time with the power-on VCC signal, so it is biased at VCCand then the PMOS transistor 314 is off. During the ESD transition (fromlow to high), the gate voltage of the PMOS transistor 314 can not followup in time with the ESD signal, i.e. the voltage at node 2 is biased ata low voltage level, so the PMOS transistor 314 is on.

The PMOS transistor 315 will be turned on if the |Vgs| of the PMOStransistor 315 is greater than its threshold voltage, so the initial ESDcurrent is discharge from the VCC line through the PMOS transistor 314and the PMOS transistor 315 to bias the ESD protection device 320. Onthe other hand, the NMOS transistor 317 is off during the ESD event dueto the node 3 is floating and the |Vgs| of the NMOS transistor 317 issmaller than its threshold voltage, in addition, the voltage at node 5is being kept at a high voltage level.

Therefore, when the ESD event is applied to the VCC line with VSSgrounded and other nodes are floating, the ESD detection circuit 310detects the high voltage at node 5 and triggers on the ESD protectiondevice 320 such that the ESD energy is fully discharged through the ESDprotection device 320.

The ESD protection device 320 can be field oxide device (FOD) as seen inFIG. 4, which is another preferred embodiment of the present inventionusing a FOD as the ESD protection device of FIG. 3. The FOD 410 isconnected to the VCC line by one end thereof and to the grounded VSS byanother end thereof, and the substrate of the FOD 410 is coupled to thenode 5 which is acted as the trigger end of the ESD protection device320.

FIG. 7 is the spice simulation of FIG. 4 under normal VCC power-ontransition. From the simulation results, the voltage drops on the gateoxides of these devices do indeed not induce the gate oxide reliabilityissue and steady leakage current problem. FIG. 8 is the spice simulationof FIG. 4 under PS-mode ESD-zapping condition. The drain voltage of thePMOS transistor 315, that is the base voltage of parasitic bipolartransistor, can be raised up to trigger on the bipolar quickly underESD-zapping condition.

As seen in FIG. 7 where the VCC is 3.3 V, all the drain voltages and thesource voltages of the PMOS transistors 314, 315, 316 and the NMOStransistor 317 in steady state will not exceed 1V, therefore, the |Vgs|and |Vgd| of the PMOS transistors 314, 315, 316 are all smaller than2.5V such that gate oxide reliability issue and steady leakage currentproblem will not be induced.

As seen in FIG. 8, the drain voltage of the PMOS transistor 315 israised up promptly to provide a substrate-triggered current such thatthe parasitic NPN transistor of the FOD 410 is triggered on to quicklydischarge the ESD energy

Since the ESD current still is possible charge the floated VDD line thatenables the NMOS transistor 317 in active state, it is noted that if theNMOS transistor 317 is on during ESD event, the base voltage ofparasitic NPN transistor will be pulled down to zero, that is, thevoltage at the node 5 is being pulled down to zero, that causes the ESDprotection device is hard to trigger on by the ESD detection circuit310. Therefore, another NMOS transistor is being added to avoid that theunexpected ESD current path will charge up the VDD line to make the NMOStransistor 317 on as seen in FIG. 5.

Please refer to FIG. 5, which is a schematic diagram showing apower-rail ESD clamp circuit for mixed-voltage I/O buffer according toanother preferred embodiment of the present invention. When the ESDevent is applied to the VCC line with VSS grounded and other nodes arefloating, the unexpected ESD current path charges up the VDD line tomake the voltage at the node 3 is at a high voltage level, the NMOStransistor 510 is on to pull down the voltage level of the node 3 tozero voltage level to avoid the NMOS transistor 317 being turned onunexpectedly.

Since the NMOS transistor 510 is being arranged between the VCC line andthe grounded VSS to avoid the NMOS transistor 317 being turned onunexpectedly, the NMOS transistor 510 not only can be a thick gate oxideNMOS transistor with high threshold voltage, but also can be a thin gateoxide NMOS transistor with lower threshold voltage so as to be turned oneasier and faster. Please refer to FIG. 6, which is a schematic diagramshowing a power-rail ESD clamp circuit using a thin gate oxide NMOStransistor 610 instead of the thick gate oxide NMOS transistor 510 ofFIG. 5. The thin gate oxide NMOS transistor 610 with lower thresholdvoltage of FIG. 6 is easier to be turned on during ESD events.

In addition, the ESD protection device 320 not only can be a field oxidedevice (FOD), but also can be a stacked NMOS configuration, or a siliconcontrolled rectifier (SCR).

FIG. 9 shows another embodiment of the power-rail ESD protectioncircuit, where the ESD protection device is the stacked NMOSconfiguration. The stacked NMOS configuration contains two 2.5-V thickgate oxide NMOS transistors 910, 920. The gate of top NMOS transistor910 is biased at 1V through a resistor 930 and the gate of bottom NMOStransistor 920 is connected to VSS. Under such stacked NMOSconfiguration, the shared N+ diffusion region 940 will be biased atVDD−Vth_(—)2.5V during normal circuit operating condition. So, thestacked NMOS, the ESD protection device, will not have the gate-oxidereliability issue.

However, under ESD-zapping conditions, the ESD detection circuit willprovide the substrate-triggered current to trigger on the parasitic NPNinherent in stacked NMOS for bipolar action quickly as well as FIG. 6.

Furthermore, the stacked NMOS configuration can be designed as one 2.5-VNMOS transistor (top) 1010 and one 1-V NMOS transistor (bottom) 1020,which is shown in FIG. 10. Similar to the description of FIG. 9, theshared N+ diffusion region 940 will be biased at 0.7V. Such stacked NMOSconfiguration also has no gate-oxide reliability issue during normalcircuit operating condition and will provide the substrate-triggeredcurrent to trigger on the parasitic NPN inherent in stacked NMOS forbipolar action quickly under ESD-zapping conditions.

FIG. 11 shows the alternative design, where the ESD protection device isthe SCR 1110 with diode string 1120. The SCR 1110 is consisted of aresistor 1113, a PNP bipolar transistor 1115 and a NPN bipolartransistor 1117. The diode string 1120 is used to raise the totalholding voltage of SCR device 1110 to avoid the latchup issue. Thenumber of diode string is dependent on the maximum power supply voltage.For free to latchup issue, the total holding voltage of ESD protectiondevice must be designed greater than the maximum power supply voltage.

Under normal operating conditions, since the SCR 1110 is primarilyconsisted of the PNP bipolar transistor 1115 and the NPN bipolartransistor 1117, the gate oxide reliability issue and steady leakagecurrent problem will not be induced.

Under ESD-zapping conditions, the ESD detection circuit 310 alsoprovides the substrate-triggered current to bias the NPN transistor1117. As long as the base-emitter voltage is over 0.7V, the NPN 1117will be triggered on and provide the well current to trigger on the PNPtransistor 1115. Through the positive-feedback generation mechanism, SCR1110 can be triggered on at lower trigger voltage level. The ESD currentcan be discharged through the SCR path and diode string.

From the above description, the power-rail ESD clamp circuit formixed-voltage I/O buffer of the present invention has advantages asfollowing:

-   -   1. While ESD devices of different specifications are being used        in the power-rail ESD clamp circuit for mixed-voltage I/O buffer        of the present invention, each the carrying voltage of each ESD        devices is within the threshold voltage of the same. Therefore,        the gate oxide reliability issue and steady leakage current        problem will not be induced.    -   2. While ESD devices of different specifications are being used        in the power-rail ESD clamp circuit for mixed-voltage I/O buffer        of the present invention, the design of RC delay of the ESD        detection circuit will enable the ESD protection device to be        triggered on promptly such that the present invention will have        better ESD endurance and electrical characteristics comparing to        prior art.

To sum up, the present invention provides a power-rail ESD clamp circuitfor mixed-voltage I/O buffer using ESD devices of differentspecifications and specified layout capable of not only solving theissue of thin gate oxide reliability, but also discharging the ESDenergy quickly and having better ESD endurance and electricalcharacteristics.

While the preferred embodiment of the invention has been set forth forthe purpose of disclosure, modifications of the disclosed embodiment ofthe invention as well as other embodiments thereof may occur to thoseskilled in the art. Accordingly, the appended claims are intended tocover all embodiments which do not depart from the spirit and scope ofthe invention.

1. A power-rail ESD clamp circuit for mixed-voltage I/O buffercomprising: an ESD detection circuit, further comprising: a firstresistor, having a first end and a second, the first end thereof beingconnected to a first node coupled to a first voltage; a capacitor,having a first end and a second end, the first end thereof beingconnected to a second node coupled to the second end of the firstresistor; a second resistor having a first end and a second end, thefirst end thereof being connected to a second voltage; a first PMOStransistor, having a gate, a drain and a source, the gate thereof beingconnected to both a third node and the second resistor, the drainthereof being connected to a fourth node coupled to a grounded point,the source thereof being connected to the second end of the capacitor; asecond PMOS transistor, having a gate, a drain and a source, the gatethereof being connected to the second node, the source thereof beingconnected to the first node; a third PMOS transistor, having a gate, adrain and a source, the gate thereof being connected to the third node,the source thereof being connected to the drain of the second PMOStransistor; and a first NMOS transistor, having a gate, a drain and asource, the gate thereof being connected to the third node, the drainbeing connected to a fifth node coupled to the drain of the third PMOStransistor; an ESD protection device, further comprising: a first end,being connected to the first node; a second end, being connected to thefourth node; and a trigger end, being connected to the fifth end.
 2. Thepower-rail ESD clamp circuit for mixed-voltage I/O buffer of claim 1,wherein, under normal operating conditions, the first PMOS transistor,the second PMOS transistor and the third PMOS transistor are 2.5-V PMOStransistors.
 3. The power-rail ESD clamp circuit for mixed-voltage I/Obuffer of claim 2, wherein the first NMOS transistor is an 1_(—)V NMOStransistor.
 4. The power-rail ESD clamp circuit for mixed-voltage I/Obuffer of claim 1, wherein the first PMOS transistor, the second PMOStransistor and the third PMOS transistor each further comprises asubstrate, the substrate thereof being connected to a node coupled tothe source of the same.
 5. The power-rail ESD clamp circuit formixed-voltage I/O buffer of claim 1, wherein the ESD detection circuitfurther comprising: a second NMOS transistor, having a gate, a drain anda source, the gate thereof being connected to the fifth node, the drainbeing connected to the third node, the source thereof being connected tothe fourth node.
 6. The power-rail ESD clamp circuit for mixed-voltageI/O buffer of claim 5, wherein, under normal operation conditions, thefirst PMOS transistor, the second PMOS transistor, the third PMOStransistor and the second NMOS transistor are 2.5-V PMOS transistors,and the first NMOS transistor is an 1-V NMOS transistor.
 7. Thepower-rail ESD clamp circuit for mixed-voltage I/O buffer of claim 5,wherein, under normal operation conditions, the first PMOS transistor,the second PMOS transistor, and the third PMOS transistor are 2.5-V PMOStransistors, and the first NMOS transistor and the second NMOStransistor are 1-V NMOS transistors.
 8. The power-rail ESD clamp circuitfor mixed-voltage I/O buffer of claim 1, wherein the ESD protectiondevice is a NPN bipolar transistor having a collector, a emitter and abase respectively equivalent to the first end, the second end and thetrigger end of the ESD protection device.
 9. The power-rail ESD clampcircuit for mixed-voltage I/O buffer of claim 8, wherein the ESDprotection device is a field oxide device having a substrate, a firstend and a second end respectively equivalent to the trigger end, thefirst end and the second end of the ESD protection device.
 10. Thepower-rail ESD clamp circuit for mixed-voltage I/O buffer of claim 9,wherein under normal operation conditions, the first PMOS transistor,the second PMOS transistor, and the third PMOS transistor are 2.5-V PMOStransistors, the field oxide device is a 2.5-V device and the first NMOStransistor is an 1-V NMOS transistor.
 11. The power-rail ESD clampcircuit for mixed-voltage I/O buffer of claim 8, wherein the ESDprotection device is consisted of a third NMOS transistor, a fourth NMOStransistor and a third resistor, and the third NMOS transistor has agate being connected to the voltage through the third resistor, a drainand a source, and the fourth NMOS transistor has a gate being connectedto the grounded point, a drain and a source, and the third resistor hasa first end connected to the voltage and a second end connected to thegate of the third NMOS transistor, in addition, the drain of the thirdNMOS transistor acts as the first end of the ESD protection device, anda node coupled to both the gate and the source of the fourth NMOStransistor acts as the second end of the ESD protection device, and anode coupled to the source of the third NMOS transistor and the drain ofthe fourth NMOS transistor acts as the trigger end of the ESD protectiondevice.
 12. The power-rail ESD clamp circuit for mixed-voltage I/Obuffer of claim 11, wherein under normal operation conditions, the firstPMOS transistor, the second PMOS transistor, the third PMOS transistor,the third NMOS transistor and the fourth NMOS transistor are 2.5-V PMOStransistors, and the first NMOS transistor is an 1-V NMOS transistor.13. The power-rail ESD clamp circuit for mixed-voltage I/O buffer ofclaim 11, wherein under normal operation conditions, the first PMOStransistor, the second PMOS transistor, the third PMOS transistor, andthe third NMOS transistor are 2.5-V PMOS transistors, and the first NMOStransistor and the fourth NMOS transistor are 1-V NMOS transistors. 14.The power-rail ESD clamp circuit for mixed-voltage I/O buffer of claim8, wherein the ESD protection device is a silicon controlled rectifierwith diode string, the silicon controlled rectifier thereof having afirst end used as the first end of the ESD protection device, a secondend and a trigger end used as the trigger end of the ESD protectiondevice, and the diode string thereof having a first end connected to thesecond end of the silicon controlled rectifier and a second end used asthe second end of the ESD protection device.
 15. The power-rail ESDclamp circuit for mixed-voltage I/O buffer of claim 14, wherein thesilicon controlled rectifier comprises: a fourth resistor, having afirst end and a second end; a PNP bipolar transistor, having a base, acollector, and a emitter, the base thereof being coupled to a sixth nodeconnected to the second end of the fourth resistor, and the emitterthereof being coupled to a node connected to the first end of the fourthresistor where the node is the first end of the silicon controlledrectifier; and a NPN bipolar transistor, having a base, a collector, anda emitter, the base thereof being coupled to a node connected to thecollector of the PNP bipolar transistor where the node is the triggerend of the silicon controlled rectifier, the collector thereof beingcoupled to the sixth node, and the emitter being connected to the secondend of the silicon controlled rectifier.